I. Field of the Disclosure
The technology of the disclosure relates generally to computer memory systems, and more particularly to compressed memory systems configured to compress and decompress data stored in and read from compressed system memory.
II. Background
As applications executed by conventional processor-based systems increase in size and complexity, memory bandwidth may become a constraint on system performance. While available memory bandwidth may be increased through the use of wider memory communications channels, this approach may incur penalties in terms of increased cost and/or additional area required for the memory on an integrated circuit (IC). Thus, one approach to increasing memory bandwidth in a processor-based system without increasing the width of memory communication channels is through the use of data compression. A data compression system can be employed in a processor-based system to store data in a compressed format, thus increasing effective memory capacity without increasing physical memory capacity.
In this regard, some conventional data compression schemes provide a compression engine to compress data to be written to a main system memory. After performing compression, the compression engine writes the compressed data to the system memory, along with metadata that maps a virtual address of the compressed data to a physical address in the system memory where the compressed data is actually stored. The data compression scheme may also maintain lists of free memory blocks (i.e., free memory lists) in the system memory to track areas of memory in which compressed data can be stored. Each free memory list holds pointers to available memory blocks within a compressed data region of the system memory. The contents of the free memory lists may be cached in a free memory list cache of the compression engine.
However, some implementations of free memory list caches may give rise to conditions in which excessive bandwidth is consumed during maintenance of the cached free memory lists. Accordingly, it is desirable to reduce the memory bandwidth required to maintain the free memory list cache.